1. Field of the Invention
The present invention relates to programmable logic array architectures. More particularly, it relates to a single block PAL plus PLA architecture.
2. The Prior Art
The basic building blocks of a programmable logic device (Pld) are the Product-term and the ORterm. Within each of these terms exists several programmable logic blocks (cells). When the outputs of several such cells are `ANDed` the term is called a `Product-term`, and when outputs are "ORed` the term is called an `ORterm`.
The construction of a programmable logic array requires the joining of two array blocks commonly known as a `PAL` and `PLA` array. The construction of the `PAL` array is made by stacking several product-terms and `ORing` sequential clusters of their outputs into a fixed width OR gate. The construction of the `PLA` array is similar to that of the `PAL` array except the output of each product-term functions as an input to an array of ORterms.
The basic PLD contains a single PAL array or PLA array, or one of each. When constructing complex PLDs (CPLDs), multiple blocks of PAL and PLA arrays are used. These array structures are generally L-shaped, and as such, prevent the efficient placement of multiple blocks of these arrays on silicon. Under this circumstance, not only is silicon die space wasted, but decode routing is more complicated, and propagation delays through the PLA become more skewed.